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C8051F380/1/2/3/4/5/6/7/C
14.6. Memory Mode Selection
The external data memory space can be configured in one of four modes, shown in Figure 14.4, based on
the EMIF Mode bits in the EMI0CF register (SFR Definition 14.5). These modes are summarized below.
More information about the different modes can be found in Section “14.7. Timing” on page 102.
EMI0CF[3:2] = 00
0xFFFF
EMI0CF[3:2] = 01
0xFFFF
EMI0CF[3:2] = 10
0xFFFF
EMI0CF[3:2] = 11
0xFFFF
On-Chip XRAM
On-Chip XRAM
Off-Chip
Memory
(No Bank Select)
Off-Chip
Memory
(Bank Select)
On-Chip XRAM
Off-Chip
Memory
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
0x0000
0x0000
0x0000
0x0000
Figure 14.4. EMIF Operating Modes
14.6.1. Internal XRAM Only
When EMI0CF.[3:2] are set to 00, all MOVX instructions will target the internal XRAM space on the device.
Memory accesses to addresses beyond the populated space will wrap on 2k or 4k boundaries (depending
on the RAM available on the device). As an example, the addresses 0x1000 and 0x2000 both evaluate to
address 0x0000 in on-chip XRAM space.
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?
8-bit MOVX operations use the contents of EMI0CN to determine the high-byte of the effective address
and R0 or R1 to determine the low-byte of the effective address.
16-bit MOVX operations use the contents of the 16-bit DPTR to determine the effective address.
14.6.2. Split Mode without Bank Select
When EMI0CF.[3:2] are set to 01, the XRAM memory map is split into two areas, on-chip space and
off-chip space.
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Effective addresses below the internal XRAM size boundary will access on-chip XRAM space.
Effective addresses above the internal XRAM size boundary will access off-chip space.
8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is
on-chip or off-chip. However, in the “No Bank Select” mode, an 8-bit MOVX operation will not drive the
upper 8-bits A[15:8] of the Address Bus during an off-chip access. This allows the user to manipulate
the upper address bits at will by setting the Port state directly via the port latches. This behavior is in
contrast with “Split Mode with Bank Select” described below. The lower 8-bits of the Address Bus A[7:0]
are driven, determined by R0 or R1.
16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-chip
or off-chip, and unlike 8-bit MOVX operations, the full 16-bits of the Address Bus A[15:0] are driven
during the off-chip transaction.
100
Rev. 1.4
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